ADT7518
Rev. A | Page 26 of 40
UNLOCK ASSOCIATED
MSB REGISTERS
SECOND READ
COMMAND
MSB
REGISTER
OUTPUT
DATA
Figure 52. Phase 2 of 10-Bit Read
If an MSB register is read first, its corresponding LSB register is
not locked, leaving the user with the option of just reading back
8 bits (MSB) of a 10-bit conversion result. Reading an MSB
register first does not lock other MSB registers, and likewise
reading an LSB register first does not lock other LSB registers.
Table 10. ADT7518 Registers
RD/WR
Address
Name
Power-On
Default
00h
Interrupt Status 1
00h
01h
Interrupt Status 2
00h
02h
Reserved
03h
Internal Temp and V
DD
LSBs
00h
04h
External Temp and AIN1 to AIN4 LSBs
00h
05h
Reserved
00h
06h
V
DD
MSBs
xxh
07h
Internal Temp MSBs
00h
08h
External Temp MSBs/AIN1 MSBs
00h
09h
AIN2 MSBs
00h
0Ah
AIN3 MSBs
00h
0Bh
AIN4 MSBs
00h
0Ch10h
Reserved
00h
11h
DAC A MSBs
00h
12h
Reserved
00h
13h
DAC B MSBs
00h
14h
Reserved
00h
15h
DAC C MSBs
00h
16h
Reserved
00h
17h
DAC D MSBs
00h
18h
Control Configuration 1
00h
19h
Control Configuration 2
00h
1Ah
Control Configuration 3
00h
1Bh
DAC Configuration
00h
1Ch
LDAC Configuration
00h
1Dh
Interrupt Mask 1
00h
1Eh
Interrupt Mask 2
00h
1Fh
Internal Temp Offset
00h
20h
External Temp Offset
00h
21h
Internal Analog Temp Offset
D8h
22h
External Analog Temp Offset
D8h
23h
VDD VHIGH Limit
C7h
24h
VDD VLOW Limit
62h
25h
Internal THIGH Limit
64h
26h
Internal TLOW Limit
C9h
27h
External THIGH/AIN1 VHIGH Limits
FFh
28h
External TLOW/AIN1 VLOW Limits
00h
29h2Ah
Reserved
2Bh
AIN2 VHIGH Limit
FFh
2Bh
AIN2 VHIGH Limit
FFh
2Ch
AIN2 V
LOW
Limit
00h
2Dh
AIN3 V
HIGH
Limit
FFh
2Eh
AIN3 V
LOW
Limit
00h
RD/WR
Address
Name
Power-On
Default
2Fh
AIN4 V
HIGH
Limit
FFh
30h
AIN4 V
LOW
Limit
00h
31h4Ch
Reserved
4Dh
Device ID
03h/0Bh/
07h
4Eh
Manufacturers ID
41h
4Fh
Silicon Revision
04h
50h7Eh
Reserved
00h
7Fh
SPI Lock Status
00h
80hFFh
Reserved
00h
Interrupt Status 1 Register (Read-Only) [Address = 00h]
This 8-bit read-only register reflects the status of some of the
interrupts that can cause the INT/INT
pin to go active. This
register is reset by a read operation, provided that any out-of-
limit event has been corrected. It is also reset by a software reset.
Table 11. Interrupt Status 1 Register
D7
D6
D5
D4
D3
D2
D1
D0
0*
0*
0*
0*
0*
0*
0*
0*
*Default settings at power-up
Table 12.
Bit Function
D0 1 when the internal temperature value exceeds THIGH limit. Any
internal temperature reading greater than the set limit will
cause an out-of-limit event.
D1 1 when internal temperature value exceeds TLOW limit. Any
internal temperature reading less than or equal to the set limit
will cause an out-of-limit event.
D2 This status bit is linked to the configuration of Pins 7 and 8. If
configured for the external temperature sensor, this bit is 1
when the external temperature value the exceeds THIGH limit.
The default value for this limit register is 1癈, so any external
temperature reading greater than the set limit will cause an
out-of-limit event. If configured for AIN1 and AIN2, this bit is 1
when AIN1 input voltage exceeds VHIGH or VLOW limits.
D3 1 when external temperature value exceeds T
LOW
limit. The
default value for this limit register is 0癈, so any external
temperature reading less than or equal to the set limit will
cause an out-of-limit event.
D4 1 Indicates a fault (open or short) for the external temperature
sensor.
D5 1 when AIN2 voltage is greater than its corresponding VHIGH
limit. 1 when AIN2 voltage is less than or equal to its
corresponding VLOW limit.
D6 1 when AIN3 voltage is greater than its corresponding V
HIGH
limit. 1 when AIN3 voltage is less than or equal to its
corresponding V
LOW
limit.
D7 1 when AIN4 voltage is greater than its corresponding VHIGH
limit. 1 when AIN4 voltage is less than or equal to its
corresponding VLOW limit.
Interrupt Status 2 Register (Read-Only) [Address = 01h]
This 8-bit read-only register reflects the status of the V
DD
inter-
rupt that can cause the INT/
INT
pin to go active. This register is
reset by a read operation, provided that any out-of-limit event
has been corrected. It is also reset by a software reset.
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